@article {19273,
	title = {Dataflow-Based Implementation of Layered Sensing Applications},
	year = {2011},
	month = {2011},
	abstract = {This report describes a new dataflow-based technology and associated design tools for high-productivity design, analysis, and optimization of layered sensing software for signal processing systems. Our approach provides novel capabilities, based on the principles of task-level dataflow analysis, for exploring and optimizing interactions across application behavior; operational context; high performance embedded processing platforms, and implementation constraints. Particularly, we introduce and deliver novel software tools, called the targeted dataflow interchange format (TDIF) and Dataflow Interchange Format Markup Language (DIFML), for design and implementation of layered sensing and signal processing systems. The TDIF-CUDA (Compute Unified Device Architecture) environment is a graphics processing unit targeted software synthesis tool that provides a unique integration of dynamic dataflow modeling; retargetable actor construction; software synthesis; and instrumentation-based schedule evaluation and tuning. The DIFML package is a software package for the DIFML format, which is an Extensible Markup Language (XML)-based format for exchanging information between DIF and other tools.},
	keywords = {*COMPUTER AIDED DESIGN, *DATA FUSION, *DATAFLOW, *LAYERS, *SOFTWARE TOOLS, COMPUTER PROGRAMMING AND SOFTWARE, DETECTION, High performance computing, LAYERED SENSING, OPTIMIZATION, Signal processing, synthesis, T2KA},
	author = {Bhattacharyya, Shuvra S. and Chung-Ching Shen and Plishker,William and Sane, Nimish and Wu, Hsiang-Huang and Gu, Ruirui}
}
@inbook {19277,
	title = {Heterogeneous Design in Functional DIF},
	booktitle = {Transactions on High-Performance Embedded Architectures and Compilers IV},
	series = {Lecture Notes in Computer Science},
	year = {2011},
	month = {2011},
	pages = {391 - 408},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	abstract = {Dataflow formalisms have provided designers of digital signal processing (DSP) systems with analysis and optimizations for many years. As system complexity increases, designers are relying on more types of dataflow models to describe applications while retaining these implementation benefits. The semantic range of DSP-oriented dataflow models has expanded to cover heterogeneous models and dynamic applications, but efficient design, simulation, and scheduling of such applications has not. To facilitate implementing heterogeneous applications, we utilize a new dataflow model of computation and show how actors designed in other dataflow models are directly supported by this framework, allowing system designers to immediately compose and simulate actors from different models. Using examples, we show how this approach can be applied to quickly describe and functionally simulate a heterogeneous dataflow-based application such that a designer may analyze and tune trade-offs among different models and schedules for simulation time, memory consumption, and schedule size.},
	keywords = {Arithmetic and Logic Structures, Computer Communication Networks, Dataflow, heterogeneous, Input/Output and Data Communications, Logic Design, Processor Architectures, Programming Languages, Compilers, Interpreters, Signal processing},
	isbn = {978-3-642-24567-1, 978-3-642-24568-8},
	url = {http://link.springer.com/chapter/10.1007/978-3-642-24568-8_20},
	author = {Plishker,William and Sane, Nimish and Kiemb, Mary and Bhattacharyya, Shuvra S.},
	editor = {Stenstr{\"o}m, Per}
}
@conference {19262,
	title = {Methods for design and implementation of dynamic signal processing systems},
	booktitle = {2011 International Conference on Embedded Computer Systems (SAMOS)},
	year = {2011},
	month = {2011},
	pages = {i - i},
	abstract = {Summary form only given. Dynamic signal processing systems, where significant changes in functionality and computational structure must be achieved while applications are running, are becoming increasingly important as computational platforms become more powerful, and feature-sets of DSP-powered products become more sophisticated. This talk covers two new, complementary dataflow models of computation that are being developed in the Maryland DSPCAD Research Group to help address the challenges of structured design, simulation, and synthesis of dynamic signal processing systems. The first of these models, called enable-invoke dataflow (EIDF), is aimed improving the predictability of actor invocation and the efficiency with which dynamic scheduling techniques can be realized. The second model, called the dataflow schedule graph (DSG), provides a formal framework for representing and analyzing dataflow graph schedules that is rooted in formal dataflow semantics, and accommodates a wide range of schedule classes, including static, quasi-static, and dynamic schedules, as well as both sequential and parallel schedule formats. In this talk, I will present the EIDF and DSG models and discuss their potential to improve the processes by which dynamic signal processing systems are developed.},
	keywords = {actor invocation predictability, complementary dataflow models, Computational modeling, computational structure, COMPUTERS, data flow graphs, dataflow schedule graph, DSG models, DSP-powered products, Dynamic scheduling, dynamic scheduling techniques, dynamic signal processing systems, Educational institutions, EIDF models, enable-invoke dataflow, formal dataflow semantics, functionality structure, Laboratories, Maryland DSPCAD Research Group, quasi-static schedules, Schedules, scheduling, Signal processing, static schedules},
	author = {Bhattacharyya, Shuvra S.}
}
@conference {19270,
	title = {A Model-Based Schedule Representation for Heterogeneous Mapping of Dataflow Graphs},
	booktitle = {2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)},
	year = {2011},
	month = {2011},
	pages = {70 - 81},
	abstract = {Dataflow-based application specifications are widely used in model-based design methodologies for signal processing systems. In this paper, we develop a new model called the dataflow schedule graph (DSG) for representing a broad class of dataflow graph schedules. The DSG provides a graphical representation of schedules based on dataflow semantics. In conventional approaches, applications are represented using dataflow graphs, whereas schedules for the graphs are represented using specialized notations, such as various kinds of sequences or looping constructs. In contrast, the DSG approach employs dataflow graphs for representing both application models and schedules that are derived from them. Our DSG approach provides a precise, formal framework for unambiguously representing, analyzing, manipulating, and interchanging schedules. We develop detailed formulations of the DSG representation, and present examples and experimental results that demonstrate the utility of DSGs in the context of heterogeneous signal processing system design.},
	keywords = {Computational modeling, data flow graphs, dataflow schedule graph, dataflow semantics, dataflow-based application specifications, Dynamic scheduling, heterogeneous mapping, heterogeneous signal processing system design, model-based design methodologies, model-based schedule representation, Processor scheduling, Program processors, Schedules, semantics, Signal processing, synchronization},
	author = {Wu, Hsiang-Huang and Chung-Ching Shen and Sane, N. and Plishker,W. and Bhattacharyya, Shuvra S.}
}
@conference {19261,
	title = {Modeling and optimization of dynamic signal processing in resource-aware sensor networks},
	booktitle = {2011 8th IEEE International Conference on Advanced Video and Signal-Based Surveillance (AVSS)},
	year = {2011},
	month = {2011},
	pages = {449 - 454},
	abstract = {Sensor node processing in resource-aware sensor networks is often critically dependent on dynamic signal processing functionality - i.e., signal processing functionality in which computational structure must be dynamically assessed and adapted based on time-varying environmental conditions, operating constraints or application requirements. In dynamic signal processing systems, it is important to provide flexibility for run-time adaptation of application behavior and execution characteristics, but in the domain of resource-aware sensor networks, such flexibility cannot come with significant costs in terms of power consumption overhead or reduced predictability. In this paper, we review a variety of complementary models of computation that are being developed as part of the dataflow interchange format (DIF) project to facilitate efficient and reliable implementation of dynamic signal processing systems. We demonstrate these methods in the context of resource-aware sensor networks.},
	keywords = {Adaptation models, Aerodynamics, Computational modeling, data flow graphs, dataflow interchange format, Dynamic scheduling, dynamic signal processing, power consumption overhead, Program processors, resource-aware sensor networks, run-time adaptation, Schedules, sensor node processing, Signal processing, Wireless sensor networks},
	author = {Bhattacharyya, Shuvra S. and Plishker,W. and Sane, N. and Chung-Ching Shen and Wu, Hsiang-Huang}
}
@conference {19281,
	title = {Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays},
	booktitle = {2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)},
	year = {2010},
	month = {2010},
	pages = {2121 - 2125},
	abstract = {Processing structures based on arrays of computational elements form an important class of architectures, which includes field programmable gate arrays (FPGAs), systolic arrays, and various forms of multicore processors. A wide variety of design methods and tools have been targeted to regular processing arrays involving homogeneous processing elements. In this paper, we introduce the concept of field programmable X arrays (FPXAs) as an abstract model for design and implementation of heterogeneous multiprocessor arrays for signal processing systems. FPXAs are abstract structures that can be targeted for implementation on application-specific integrated circuits, FPGAs, or other kinds of reconfigurable processors. FPXAs can also be mapped onto multicore processors for flexible emulation. We discuss the use of dataflow models as an integrated application representation and intermediate representation for efficient specification and mapping of signal processing systems on FPXAs. We demonstrate our proposed models and techniques with a case study involving the embedding of an application-specific FPXA system on an off-the-shelf FPGA device.},
	keywords = {application specific integrated circuits, application-specific integrated circuits, computational elements, Computer architecture, decoding, Field programmable gate arrays, field programmable X arrays, FPGA, FPXA, Integrated circuit modeling, Logic Design, microprocessor chips, multicore processors, multiprocessor arrays, real-time signal processing, reconfigurable architectures, reconfigurable processors, Routing, Signal processing, Signal processing systems, systolic arrays, Viterbi algorithm},
	author = {Wu, Hsiang-Huang and Chung-Ching Shen and Bhattacharyya, Shuvra S. and Compton, K. and Schulte, M. and Wolf, M. and Zhang, Tong}
}
@conference {19285,
	title = {Scalable representation of dataflow graph structures using topological patterns},
	booktitle = {2010 IEEE Workshop on Signal Processing Systems (SIPS)},
	year = {2010},
	month = {2010},
	pages = {13 - 18},
	abstract = {Tools for designing signal processing systems with their semantic foundation in dataflow modeling often use high-level graphical user interface (GUI) or text based languages that allow specifying applications as directed graphs. Such graphical representations serve as an initial reference point for further analysis and optimizations that lead to platform-specific implementations. For large-scale applications, the underlying graphs often consist of smaller substructures that repeat multiple times. To enable more concise representation and direct analysis of such substructures in the context of high level DSP specification languages and design tools, we develop the modeling concept of topological patterns, and propose ways for supporting this concept in a high-level language. We augment the DIF language - a language for specifying DSP-oriented dataflow graphs - with constructs for supporting topological patterns, and we show how topological patterns can be effective in various aspects of embedded signal processing design flows using specific application examples.},
	keywords = {arrays, data flow graphs, Dataflow graphs, DIF language, Digital signal processing, directed graphs, DSP specification languages, embedded signal processing design flows, embedded systems, Field programmable gate arrays, graphical user interface, Graphical user interfaces, High-level languages, modelbased design, optimisation, optimizations, scalable dataflow graph structures representation, semantics, Signal processing, Signal processing systems, Specification languages, text based languages, Topological patterns, Topology, Transform coding},
	author = {Sane, N. and Kee, Hojin and Seetharaman, G. and Bhattacharyya, Shuvra S.}
}
@article {19298,
	title = {Signal Processing on Platforms with Multiple Cores: Part 2-Applications and Design [From the Guest Editors]},
	journal = {IEEE Signal Processing Magazine},
	volume = {27},
	year = {2010},
	month = {2010},
	pages = {20 - 21},
	abstract = {Platforms with multiple cores are now prevalent everywhere from desktops and graphics processors to laptops and embedded systems. By adding more parallel computational resources while managing power consumption, multicore platforms offer better programmability, performance, and power efficiency. Signal processing systems of tomorrow will be and must be implemented on platforms with multiple cores. Writing efficient parallel applications that utilize the computing capability of many processing cores require some effort. Signal processing algorithm designers must understand the nuances of a multicore computing engine; only then can the tremendous computing power that such platforms provide be harnessed efficiently. To give a thorough perspective of the area, we have organized two special issues on this topic.},
	keywords = {Concurrent computing, Embedded system, Energy management, Graphics, Multicore processing, Portable computers, Resource management, Signal design, Signal processing, Signal processing algorithms},
	isbn = {1053-5888},
	author = {Chen,Y. and Chakrabarti,C. and Bhattacharyya, Shuvra S. and Bougard, B.}
}
@conference {19296,
	title = {Simulating dynamic communication systems using the core functional dataflow model},
	booktitle = {2010 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP)},
	year = {2010},
	month = {2010},
	pages = {1538 - 1541},
	abstract = {The latest communication technologies invariably consist of modules with dynamic behavior. There exists a number of design tools for communication system design with their foundation in dataflow modeling semantics. These tools must not only support the functional specification of dynamic communication modules and subsystems but also provide accurate estimation of resource requirements for efficient simulation and implementation. We explore this trade-off - between flexible specification of dynamic behavior and accurate estimation of resource requirements - using a representative application employing an adaptive modulation scheme. We propose an approach for precise modeling of such applications based on a recently-introduced form of dynamic dataflow called core functional dataflow. From our proposed modeling approach, we show how parameterized looped schedules can be generated and analyzed to simulate applications with low run-time overhead as well as guaranteed bounded memory execution. We demonstrate our approach using the Advanced Design System from Agilent Technologies, Inc., which is a commercial tool for design and simulation of communication systems.},
	keywords = {adaptive modulation, Analytical models, Application software, Computational modeling, core functional dataflow model, Dataflow, dataflow modeling semantics, design tools, Digital signal processing, dynamic communication systems, functional specification, Hardware, modeling and simulation, Power system modeling, Predictive models, Processor scheduling, Production, Signal processing, software tools, wireless communication},
	author = {Sane, N. and Chia-Jui Hsu and Pino,J. L and Bhattacharyya, Shuvra S.}
}
@article {12352,
	title = {Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation},
	journal = {IEEE Transactions on Signal Processing},
	volume = {55},
	year = {2007},
	month = {2007/06//},
	pages = {3126 - 3138},
	abstract = {In this paper, we present a technique for compact representation of execution sequences in terms of efficient looping constructs. Here, by a looping construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression},
	keywords = {Application software, array signal processing, code compression methodology, compact representation, Compaction, data compression, Design automation, Digital signal processing, digital signal processing chips, DSP, DSP hardware, embedded systems, Encoding, Field programmable gate arrays, field-programmable gate arrays (FPGAs), FPGA, Hardware, hierarchical runlength encoding, high-level synthesis, Kahn process, loop-based code compaction, looping construct, parameterized loop schedules, program compilers, reconfigurable design, runlength codes, scheduling, Signal generators, Signal processing, Signal synthesis, software engineering, software implementation, static dataflow models, Very large scale integration, VLSI},
	isbn = {1053-587X},
	doi = {10.1109/TSP.2007.893964},
	author = {Ming-Yung Ko and Zissulescu,C. and Puthenpurayil,S. and Bhattacharyya, Shuvra S. and Kienhuis,B. and Deprettere,E. F}
}
@conference {12347,
	title = {A Communication Interface for Multiprocessor Signal Processing Systems},
	booktitle = {Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia},
	year = {2006},
	month = {2006/10//},
	pages = {127 - 132},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Parallelization of embedded software is often desirable for power/performance-related considerations for computation-intensive applications that frequently occur in the signal-processing domain. Although hardware support for parallel computation is increasingly available in embedded processing platforms, there is a distinct lack of effective software support. One of the most widely known efforts in support of parallel software is the message passing interface (MPI). However, MPI suffers from several drawbacks with regards to customization to specialized parallel processing contexts, and performance degradation for communication-intensive applications. In this paper, we propose a new interface, the signal passing interface (SPI), that is targeted toward signal processing applications and addresses the limitations of MPI for this important domain of embedded software by integrating relevant properties of MPI and coarse-grain dataflow modeling. SPI is much easier and more intuitive to use, and due to its careful specialization, more performance-efficient for the targeted application domain. We present our preliminary version of SPI, along with experiments using SPI on a practical face detection system that demonstrate the capabilities of SPI},
	keywords = {application program interfaces, Application software, coarse-grain dataflow modeling, Computer applications, Concurrent computing, Context, data flow graphs, Embedded computing, Embedded software, face detection system, Hardware, Message passing, message passing interface, MPI, Multiprocessing systems, multiprocessor signal processing system, PARALLEL PROCESSING, signal passing interface, Signal processing, SPI},
	isbn = {0-7803-9783-5},
	doi = {10.1109/ESTMED.2006.321285},
	author = {Sankalita Saha and Bhattacharyya, Shuvra S. and Wayne Wolf}
}
@article {12378,
	title = {Contention-conscious transaction ordering in multiprocessor DSP systems},
	journal = {IEEE Transactions on Signal Processing},
	volume = {54},
	year = {2006},
	month = {2006/02//},
	pages = {556 - 569},
	abstract = {This paper explores the problem of efficiently ordering interprocessor communication (IPC) operations in statically scheduled multiprocessors for iterative dataflow graphs. In most digital signal processing (DSP) applications, the throughput of the system is significantly affected by communication costs. By explicitly modeling these costs within an effective graph-theoretic analysis framework, we show that ordered transaction schedules can significantly outperform self-timed schedules even when synchronization costs are low. However, we also show that when communication latencies are nonnegligible, finding an optimal transaction order given a static schedule is an NP-complete problem, and that this intractability holds both under iterative and noniterative execution. We develop new heuristics for finding efficient transaction orders, and perform an extensive experimental comparison to gauge the performance of these heuristics.},
	keywords = {contention-conscious transaction ordering, Costs, data flow graphs, Dataflow, Delay, Digital signal processing, digital signal processing chips, Embedded system, graph-theoretic analysis, Instruments, Internet telephony, interprocessor communication, iterative dataflow graphs, iterative methods, Message passing, multiprocessor, multiprocessor DSP systems, NP-complete problem, Processor scheduling, scheduling, Signal processing, synchronization, Throughput},
	isbn = {1053-587X},
	doi = {10.1109/TSP.2005.861074},
	author = {Khandelia,M. and Bambha,N. K and Bhattacharyya, Shuvra S.}
}
@conference {12387,
	title = {Porting DSP applications across design tools using the dataflow interchange format},
	booktitle = {Rapid System Prototyping, 2005. (RSP 2005). The 16th IEEE International Workshop on},
	year = {2005},
	month = {2005/06//},
	pages = {40 - 46},
	abstract = {Modeling DSP applications through coarse-grain dataflow graphs is popular in the DSP design community, and a growing set of rapid prototyping tools support such dataflow semantics. Since different tools may be suitable for different phases or generations of a design, it is often desirable to migrate a dataflow-based application model from one prototyping tool to another. Two critical problems in transferring dataflow-based designs across different prototyping tools are the lack of a vendor-independent language for DSP-oriented dataflow graphs, and the lack of an efficient porting methodology. In our previous work, the dataflow interchange format (DIF) (C. Hsu et al., 2004) has been developed as a standard language to specify mixed-grain dataflow models for DSP systems. This paper presents the augmentation of the DIF infrastructure with a systematic porting approach that integrates DIF tightly with the specific exporting and importing mechanisms that interface DIF to specific DSP design tools. In conjunction with this porting mechanism, this paper also introduces a novel language, called the actor interchange format (AIF), for transferring relevant information pertaining to DSP library components across different tools. Through a case study of a synthetic aperture radar application, we demonstrate the high degree of automation offered by our DIF-based porting approach.},
	keywords = {actor interchange format, coarse-grain dataflow graph, data flow analysis, data flow graphs, dataflow interchange format, dataflow model, dataflow semantic, DSP application, DSP design tool, DSP library component, electronic data interchange, formal specification, rapid prototyping tool, Signal processing, software prototyping, Specification languages, vendor-independent language},
	doi = {10.1109/RSP.2005.39},
	author = {Hsu,C.-J. and Bhattacharyya, Shuvra S.}
}
@article {18462,
	title = {Processing of reverberant speech for time-delay estimation},
	journal = {IEEE Transactions on Speech and Audio Processing},
	volume = {13},
	year = {2005},
	month = {2005/11//},
	pages = {1110 - 1118},
	abstract = {In this paper, we present a method of extracting the time-delay between speech signals collected at two microphone locations. Time-delay estimation from microphone outputs is the first step for many sound localization algorithms, and also for enhancement of speech. For time-delay estimation, speech signals are normally processed using short-time spectral information (either magnitude or phase or both). The spectral features are affected by degradations in speech caused by noise and reverberation. Features corresponding to the excitation source of the speech production mechanism are robust to such degradations. We show that these source features can be extracted reliably from the speech signal. The time-delay estimate can be obtained using the features extracted even from short segments (50-100 ms) of speech from a pair of microphones. The proposed method for time-delay estimation is found to perform better than the generalized cross-correlation (GCC) approach. A method for enhancement of speech is also proposed using the knowledge of the time-delay and the information of the excitation source.},
	keywords = {Acoustic noise, acoustic signal processing, array signal processing, data mining, Degradation, delay estimation, Feature extraction, Hilbert envelope, localization algorithm, microphone arrays, microphone location, Microphones, Phase estimation, reverberation, short-time spectral information, Signal processing, source features, source information excitation, speech enhancement, Speech processing, speech production mechanism, speech signal, time-delay, time-delay estimation},
	isbn = {1063-6676},
	doi = {10.1109/TSA.2005.853005},
	author = {Yegnanarayana,B. and Prasanna,S. R.M and Duraiswami, Ramani and Zotkin,Dmitry N}
}
@conference {12393,
	title = {Systematic exploitation of data parallelism in hardware synthesis of DSP applications},
	booktitle = {Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP {\textquoteright}04). IEEE International Conference on},
	volume = {5},
	year = {2004},
	month = {2004/05//},
	pages = {V - 229-32 vol.5 - V - 229-32 vol.5},
	abstract = {We describe an approach that we have explored for low-power synthesis and optimization of image, video, and digital signal processing (DSP) applications. In particular, we consider the systematic exploitation of data parallelism across the operations of an application dataflow graph when synthesizing a dedicated hardware implementation. Data parallelism occurs commonly in DSP applications, and provides flexible opportunities to increase throughput or lower power consumption. Exploiting this parallelism in a dedicated hardware implementation comes at the expense of increased resource requirements, which must be balanced carefully when applying the technique in a design tool. We propose a high level synthesis algorithm to determine the data parallelism factor for each computation, and, based on the area and performance trade-off curve, design an efficient hardware representation of the dataflow graph. For performance estimation, our approach uses a cyclostatic dataflow intermediate representation of the hardware structure under synthesis. We then apply an automatic hardware generation framework to build the actual circuit.},
	keywords = {area-performance trade-off curve, automatic Verilog code generation, circuit optimisation, data flow graphs, data parallelism, dedicated hardware implementation synthesis, design tool, Digital signal processing, DSP applications, embedded systems, hardware description languages, hardware synthesis, high level synthesis, high level synthesis algorithm, IMAGE PROCESSING, PARALLEL PROCESSING, power consumption, Signal processing, synchronous dataflow graph, video processing},
	doi = {10.1109/ICASSP.2004.1327089},
	author = {Sen,M. and Bhattacharyya, Shuvra S.}
}
@conference {17113,
	title = {Dynamic querying for pattern identification in microarray and genomic data},
	booktitle = {2003 International Conference on Multimedia and Expo, 2003. ICME {\textquoteright}03. Proceedings},
	volume = {3},
	year = {2003},
	month = {2003/07/06/9},
	pages = {III- 453-6 vol.3 - III- 453-6 vol.3},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Data sets involving linear ordered sequences are a recurring theme in bioinformatics. Dynamic query tools that support exploration of these data sets can be useful for identifying patterns of interest. This paper describes the use of one such tool - timesearcher - to interactively explore linear sequence data sets taken from two bioinformatics problems. Microarray time course data sets involve expression levels for large numbers of genes over multiple time points. Timesearcher can be used to interactively search these data sets for genes with expression profiles of interest. The occurrence frequencies of short sequences of DNA in aligned exons can be used to identify sequences that play a role in the pre-mRNA splicing. Timesearcher can be used to search these data sets for candidate splicing signals.},
	keywords = {Bioinformatics, data sets, Displays, dynamic querying, expression profiles, Frequency, Gene expression, genes, Genetics, genomic data, Genomics, linear ordered sequences, macromolecules, medical signal processing, Mice, Microarray, pattern identification, pattern recognition, premRNA splicing, Query processing, sequences, Signal processing, splicing, TimeSearcher},
	isbn = {0-7803-7965-9},
	doi = {10.1109/ICME.2003.1221346},
	author = {Hochheiser,H. and Baehrecke,E. H and Mount, Stephen M. and Shneiderman, Ben}
}
@conference {12000,
	title = {Eye design in the plenoptic space of light rays},
	booktitle = {Ninth IEEE International Conference on Computer Vision, 2003. Proceedings},
	year = {2003},
	month = {2003/10/13/16},
	pages = {1160-1167 vol.2 - 1160-1167 vol.2},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Natural eye designs are optimized with regard to the tasks the eye-carrying organism has to perform for survival. This optimization has been performed by the process of natural evolution over many millions of years. Every eye captures a subset of the space of light rays. The information contained in this subset and the accuracy to which the eye can extract the necessary information determines an upper limit on how well an organism can perform a given task. In this work we propose a new methodology for camera design. By interpreting eyes as sample patterns in light ray space we can phrase the problem of eye design in a signal processing framework. This allows us to develop mathematical criteria for optimal eye design, which in turn enables us to build the best eye for a given task without the trial and error phase of natural evolution. The principle is evaluated on the task of 3D ego-motion estimation.},
	keywords = {3D ego-motion estimation, Assembly, B-splines, Camera design, CAMERAS, captured image, compound eyes, Computer vision, data mining, eye, eye-carrying organism, Eyes, filter optimization, image representation, image resolution, Information geometry, Laboratories, light field reconstruction, light gathering power, light rays, mixed spherical-Cartesian coordinate system, Motion estimation, natural evolution process, natural eye designs, natural image statistics, optical nanotechnology, Optical signal processing, optimal eye design mathematical criteria, Organisms, plenoptic image formation, plenoptic space, plenoptic video geometry, sampling operators, sensory ecology, Signal design, Signal processing, signal processing framework, signal processing tool, square-summable sequences, visual acuity},
	isbn = {0-7695-1950-4},
	doi = {10.1109/ICCV.2003.1238623},
	author = {Neumann, J. and Ferm{\"u}ller, Cornelia and Aloimonos, J.}
}
@article {15045,
	title = {VLSI Architectures and Implementation of Predictive Tree- Searched Vector Quantizers for Real-Time Video Compression},
	volume = {ISR-TR-1992-48},
	year = {1992},
	month = {1992///},
	institution = {Institute for Systems Research, University of Maryland, College Park},
	abstract = {We describe a pipelined systolic architecture for implementing predictive Tree-Searched Vector Quantization (PTSVQ) for real- time image and speech coding applications. This architecture uses identical processors for both the encoding and decoding processes. the overall design is regular and the control is simple. Input data is processed at a rate of 1 pixel per clock cycle, which allows real-time processing of images at video rates. We implemented these processors using 1.2um CMOS technology. Spice simulations indicate correct operation at 40 MHz. Prototype version of these chips fabricated using 2um CMOS technology work at 20 MHz.},
	keywords = {data compression, IMAGE PROCESSING, Signal processing, Speech processing, Systems Integration, systolic architecture, Vector quantization, VLSI architectures},
	url = {http://drum.lib.umd.edu/handle/1903/5230},
	author = {Yu,S.-S. and Kolagotla,Ravi K. and JaJa, Joseph F.}
}
@article {15050,
	title = {VLSI Implementation of Real-Time Parallel DCT/DST Lattice Structures for Video},
	volume = {ISR-TR-1992-34},
	year = {1992},
	month = {1992///},
	institution = {Institute for Systems Research, University of Maryland, College Park},
	abstract = {The alternate use [1] of the discrete cosine transform (DCT) and the discrete sine transform (DST) can achieve a higher data compression rate and less block effect in image processing. A parallel lattice structure that can dually generate the 1-D DCT and DST is proposed. We also develop a fully-pipelined 2-D DCT lattice architecture that consists of two 1-D DCT/DST arrays without transposition. Both architectures are ideally suited for VLSI implementation because they are modular, regular, and have only local interconnections. the VLSI implementation of the lattice module using the distributed arithmetic approach is described. This realization of the lattice module using 2 um CMOS technology can achieve an 80Mb/s data rate.},
	keywords = {Parallel architectures, Signal processing, Systems Integration, VLSI architectures},
	url = {http://drum.lib.umd.edu/handle/1903/5216},
	author = {Chiu,Ching-Te and Kolagotla,Ravi K. and Liu,K. J. Ray and JaJa, Joseph F.}
}
