@conference {19281,
	title = {Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays},
	booktitle = {2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)},
	year = {2010},
	month = {2010},
	pages = {2121 - 2125},
	abstract = {Processing structures based on arrays of computational elements form an important class of architectures, which includes field programmable gate arrays (FPGAs), systolic arrays, and various forms of multicore processors. A wide variety of design methods and tools have been targeted to regular processing arrays involving homogeneous processing elements. In this paper, we introduce the concept of field programmable X arrays (FPXAs) as an abstract model for design and implementation of heterogeneous multiprocessor arrays for signal processing systems. FPXAs are abstract structures that can be targeted for implementation on application-specific integrated circuits, FPGAs, or other kinds of reconfigurable processors. FPXAs can also be mapped onto multicore processors for flexible emulation. We discuss the use of dataflow models as an integrated application representation and intermediate representation for efficient specification and mapping of signal processing systems on FPXAs. We demonstrate our proposed models and techniques with a case study involving the embedding of an application-specific FPXA system on an off-the-shelf FPGA device.},
	keywords = {application specific integrated circuits, application-specific integrated circuits, computational elements, Computer architecture, decoding, Field programmable gate arrays, field programmable X arrays, FPGA, FPXA, Integrated circuit modeling, Logic Design, microprocessor chips, multicore processors, multiprocessor arrays, real-time signal processing, reconfigurable architectures, reconfigurable processors, Routing, Signal processing, Signal processing systems, systolic arrays, Viterbi algorithm},
	author = {Wu, Hsiang-Huang and Chung-Ching Shen and Bhattacharyya, Shuvra S. and Compton, K. and Schulte, M. and Wolf, M. and Zhang, Tong}
}
@conference {19290,
	title = {Loop transformations for interface-based hierarchies IN SDF graphs},
	booktitle = {2010 21st IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP)},
	year = {2010},
	month = {2010},
	pages = {341 - 344},
	abstract = {Data-flow has proven to be an attractive computation model for programming digital signal processing (DSP) applications. A restricted version of data-flow, termed synchronous data-flow (SDF), offers strong compile-time predictability properties, but has limited expressive power. A new type of hierarchy (Interface-based SDF) has been proposed allowing more expressivity while maintaining its predictability. One of the main problems with this hierarchical SDF model is the lack of trade-off between parallelism and network clustering. This paper presents a systematic method for applying an important class of loop transformation techniques in the context of interface-based SDF semantics. The resulting approach provides novel capabilities for integrating parallelism extraction properties of the targeted loop transformations with the useful modeling, analysis, and code reuse properties provided by SDF.},
	keywords = {Application software, code generation, Computer architecture, Computer interfaces, Data-Flow programming, Digital signal processing, Loop parallelization, PARALLEL PROCESSING, Power engineering computing, Power system modeling, Processor scheduling, Programming profession, scheduling, SDF graph, system recovery},
	author = {Piat, J. and Bhattacharyya, Shuvra S. and Raulet, M.}
}
@conference {19291,
	title = {Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs},
	booktitle = {2010 21st IEEE International Symposium on Rapid System Prototyping (RSP)},
	year = {2010},
	month = {2010},
	pages = {1 - 7},
	abstract = {Parameterized Synchronous Dataflow (PSDF) has been used previously for abstract scheduling and as a model for architecting embedded software and FPGA implementations. PSDF has been shown to be attractive for these purposes due to its support for flexible dynamic reconfiguration, and efficient quasi-static scheduling. To apply PSDF techniques more deeply into the design flow, support for comprehensive functional simulation and efficient hardware mapping is important. By building on the DIF (Dataflow Interchange Format), which is a design language and associated software package for developing and experimenting with dataflow-based design techniques for signal processing systems, we have developed a tool for functional simulation of PSDF specifications. This simulation tool allows designers to model applications in PSDF and simulate their functionality, including use of the dynamic parameter reconfiguration capabilities offered by PSDF. Based on this simulation tool, we also present a systematic design methodology for applying PSDF to the design and implementation of digital signal processing systems, with emphasis on FPGA-based systems for signal processing. We demonstrate capabilities for rapid and accurate prototyping offered by our proposed design methodology, along with its novel support for PSDF-based FPGA system implementation.},
	keywords = {abstract scheduling, Computational modeling, Computer architecture, data flow graphs, dataflow based design, dataflow interchange format, design flow, design language, Digital signal processing, digital signal processing systems, dynamic parameter reconfiguration, Dynamic scheduling, efficient hardware mapping, efficient quasistatic scheduling, Embedded software, embedded systems, Field programmable gate arrays, flexible dynamic reconfiguration, FPGA based systems, FPGA implementations, functional simulation, Hardware, parameterized synchronous dataflow graphs, rapid prototyping, Schedules, scheduling, semantics, simulation tool, software package, systematic design methodology},
	author = {Wu, Hsiang-Huang and Kee, Hojin and Sane, N. and Plishker,W. and Bhattacharyya, Shuvra S.}
}
@conference {12830,
	title = {A Software Architectural Approach to Security by Design},
	booktitle = {Computer Software and Applications Conference, 2006. COMPSAC {\textquoteright}06. 30th Annual International},
	volume = {2},
	year = {2006},
	month = {2006/09/17/21},
	pages = {83 - 86},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {This paper shows how an architecture description notation that has support for timed events can be used to provide a meta-language for specifying exact communication semantics. The advantages of such an approach is that a designer is made fully aware of the ramifications of her design choices so that an attacker can no longer take advantage of hidden assumptions},
	keywords = {architecture description notation, Clocks, communication semantics, Computer architecture, computer crime, computer security, Connectors, Costs, Degradation, Delay, Educational institutions, security design, security of data, Software architecture, software engineering},
	isbn = {0-7695-2655-1},
	doi = {10.1109/COMPSAC.2006.102},
	author = {Ray,A. and Cleaveland, Rance}
}
@article {15678,
	title = {Class-based access control for distributed video-on-demand systems},
	journal = {IEEE Transactions on Circuits and Systems for Video Technology},
	volume = {15},
	year = {2005},
	month = {2005/07//},
	pages = {844 - 853},
	abstract = {The focus of this paper is the analysis of threshold-based admission control policies for distributed video-on-demand (VoD) systems. Traditionally, admission control methods control access to a resource based on the resource capacity. We have extended that concept to include the significance of an arriving request to the VoD system by enforcing additional threshold restrictions in the admission control process on request classes deemed less significant. We present an analytical model for computing blocking performance of the VoD system under threshold-based admission control. Extending the same methodology to a distributed VoD architecture we show through simulation that the threshold performance conforms to the analytical model. We also show that threshold-based analysis can work in conjunction with other request handling policies and are useful for manipulating the VoD performance since we are able to distinguish between different request classes based on their merit. Enforcing threshold restrictions with the option of downgrading blocked requests in a multirate service environment results in improved performance at the same time providing different levels of quality of service (QoS). In fact, we show that the downgrade option combined with threshold restrictions is a powerful tool for manipulating an incoming request mix over which we have no control into a workload that the VoD system can handle.},
	keywords = {Access control, Admission control, Analytical models, blocking performance, class-based access control, Computational modeling, Computer architecture, Computer science, Distributed control, Distributed video-on-demand (VoD) system, distributed video-on-demand system, multimedia systems, multirate service model, Performance analysis, QoS, quality of service, request handling policy, resource allocation, resource capacity, telecommunication congestion control, threshold-based admission control, video on demand},
	isbn = {1051-8215},
	doi = {10.1109/TCSVT.2005.848351},
	author = {Mundur, Padma and Sood,A. K and Simon,R.}
}
@article {18908,
	title = {Inferencing in Support of Active Templates},
	year = {2005},
	month = {2005/02//},
	institution = {Department of Computer Science, University of Maryland, College Park},
	abstract = {The primary accomplishments of this project include the following: (1) HICAP is a general purpose planning architecture to assist military commanders with planning NEOs (Noncombatant Evacuation Operations). HICAP integrates a hierarchical task editor with a planning tool. Military planners select a task to decompose in the task editor and then use the planning tool to interactively refine it into an operational plan. (2) SHOP and SHOP2 are some simple, practical planning tools based on HTN planning. Their practical utility is shown by the mergence of an active set of users, which include government laboratories, industrial R\&D projects, and academic settings. SHOP2 received one of the top four awards in the 2002 International Planning Competition. (3) The Air Force Research Laboratory{\textquoteright}s Causal Analysis Tool (CAT) is a system for creating and analyzing causal models similar to Bayesian networks. We have enhanced CAT by developing an approach to quickly generate plans that have high probabilities of success.},
	keywords = {*ARTILLERY AMMUNITION, *HIGH CAPACITY PROJECTILES, AMMUNITION AND EXPLOSIVES, BAYES THEOREM, COALITION, Collaboration, Computer architecture, COMPUTER HARDWARE, Computer networks, HICAP(HIGH CAPACITY ARTILLARY PROJECTILES), MILITARY COMMANDERS, NEO(NONCOMBATANT EVACUATION OPERATIONS), NONCOMBATANT., PE63760E, planning, probability, PROJECTILE TRAJECTORIES, TASK SUPPORT, WUAFRLATEMPO02},
	url = {http://stinet.dtic.mil/oai/oai?\&verb=getRecord\&metadataPrefix=html\&identifier=ADA431023},
	author = {Nau, Dana S.}
}
@conference {12078,
	title = {A secure service discovery protocol for MANET},
	booktitle = {14th IEEE Proceedings on Personal, Indoor and Mobile Radio Communications, 2003. PIMRC 2003},
	volume = {1},
	year = {2003},
	month = {2003/09/07/10},
	pages = {502- 506 Vol.1 - 502- 506 Vol.1},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Service discovery technologies are exploited to enable services to advertise their existence in a dynamic way, and can be discovered, configured and used by other devices with minimum manual efforts. It plays an essential role in future network scenarios especially with development of mobile ad hoc network (MANET) and emergence of pervasive computing. Because MANET allows these devices to communicate dynamically without fixed infrastructure and centralized administration, it gives rise to the challenges of the service discovery techniques. In this paper, we present a dynamic service discovery infrastructure that uses XML to describe services and match using the semantic content of service descriptions for MANET. We believe that the architecture we have designed is a necessary component of service discovery in non-infrastructure network by further exploring the secure and performance issues of this infrastructure.},
	keywords = {ad hoc networks, centralized administration, Computer architecture, Computer science, dynamic service discovery infrastructure, Educational institutions, MANET, Manuals, mobile ad hoc network, Mobile ad hoc networks, Mobile computing, mobile radio, noninfrastructure network, Pervasive computing, Protocols, routing protocols, secure service discovery protocol, Security, service discovery techniques, service discovery technologies, telecommunication computing, telecommunication services, XML},
	isbn = {0-7803-7822-9},
	doi = {10.1109/PIMRC.2003.1264322},
	author = {Yuan Yuan and Arbaugh, William A.}
}
@article {17849,
	title = {The virtual microscope},
	journal = {IEEE Transactions on Information Technology in Biomedicine},
	volume = {7},
	year = {2003},
	month = {2003/12//},
	pages = {230 - 248},
	abstract = {We present the design and implementation of the virtual microscope, a software system employing a client/server architecture to provide a realistic emulation of a high power light microscope. The system provides a form of completely digital telepathology, allowing simultaneous access to archived digital slide images by multiple clients. The main problem the system targets is storing and processing the extremely large quantities of data required to represent a collection of slides. The virtual microscope client software runs on the end user{\textquoteright}s PC or workstation, while database software for storing, retrieving and processing the microscope image data runs on a parallel computer or on a set of workstations at one or more potentially remote sites. We have designed and implemented two versions of the data server software. One implementation is a customization of a database system framework that is optimized for a tightly coupled parallel machine with attached local disks. The second implementation is component-based, and has been designed to accommodate access to and processing of data in a distributed, heterogeneous environment. We also have developed caching client software, implemented in Java, to achieve good response time and portability across different computer platforms. The performance results presented show that the Virtual Microscope systems scales well, so that many clients can be adequately serviced by an appropriately configured data server.},
	keywords = {biomedical optical imaging, client software, client/server architecture, Computer architecture, Computer Graphics, computer platforms, Computer simulation, Concurrent computing, configured data server, data server software, database management systems, database software, Database systems, digital slide images, digital telepathology, diseases, emulation, Environment, Equipment Design, Equipment Failure Analysis, high power light microscope, Image databases, Image Enhancement, Image Interpretation, Computer-Assisted, Image retrieval, Information retrieval, Information Storage and Retrieval, java, local disks, microscope image data, Microscopy, multiple clients, optical microscopy, PACS, software, Software design, software system, Software systems, Systems Integration, Telepathology, User-Computer Interface, virtual microscope design, Virtual reality, Workstations},
	isbn = {1089-7771},
	doi = {10.1109/TITB.2004.823952},
	author = {Catalyurek,U. and Beynon,M. D and Chang,Chialin and Kurc, T. and Sussman, Alan and Saltz, J.}
}
@conference {17080,
	title = {Developing the next generation of Earth science data systems: the Global Land Cover Facility},
	booktitle = {Geoscience and Remote Sensing Symposium, 1999. IGARSS {\textquoteright}99 Proceedings. IEEE 1999 International},
	volume = {1},
	year = {1999},
	month = {1999///},
	pages = {616-618 vol.1 - 616-618 vol.1},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {A recent initiative by NASA has resulted in the formation of a federation of Earth science data partners. These Earth Science Information Partners (ESIPs) have been tasked with creating novel Earth science data products and services as well as distributing new and existing data sets to the Earth science community and the general public. The University of Maryland established its ESIP activities with the creation of the Global Land Cover Facility (GLCF). This joint effort of the Institute for Advanced Computer Studies (UMIACS) and the Department of Geography has developed an operational data archiving and distribution system aimed at advancing current land cover research efforts. The success of the GLCF is tied closely to assessing user needs as well. As the timely delivery of data products to the research community. This paper discusses the development and implementation of a web-based interface that allows users to query the authors{\textquoteright} data holdings and perform user requested processing tasks on demand. The GLCF takes advantage of a scaleable, high performance computing architecture for the manipulation of very large remote sensing data sets and the rapid spatial indexing of multiple format data types. The user interface has been developed with the cooperation of the Human-Computer Interaction Laboratory (HCIL) and demonstrates advances in spatial and temporal querying tools as well as the ability to overlay multiple raster and vector data sets. Their work provides one perspective concerning how critical earth science data may be handled in the near future by a coalition of distributed data centers},
	keywords = {Computer architecture, data archiving, data distribution system, Data systems, Distributed computing, Earth science data products, Earth science data system, ESIP, geographic information system, geographic information systems, Geography, geophysical measurement technique, geophysical signal processing, geophysical techniques, Geoscience, GIS, GLCF, Global Land Cover Facility, High performance computing, Indexing, information service, Information services, Institute for Advanced Computer Studies, land cover, NASA, next generation, PACS, Remote sensing, terrain mapping, UMIACS, University of Maryland, User interfaces, web-based interface},
	isbn = {0-7803-5207-6},
	doi = {10.1109/IGARSS.1999.773583},
	author = {Lindsay,F.E. and Townshend,J.R.G. and JaJa, Joseph F. and Humphries,J. and Plaisant, Catherine and Shneiderman, Ben}
}
@conference {14723,
	title = {PLANet: an active internetwork},
	booktitle = {IEEE INFOCOM {\textquoteright}99. Eighteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Proceedings},
	volume = {3},
	year = {1999},
	month = {1999/03/21/25},
	pages = {1124-1133 vol.3 - 1124-1133 vol.3},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {We present PLANet: an active network architecture and implementation. In addition to a standard suite of Internet-like services, PLANet has two key programmability features: (1) all packets contain programs; and (2) router functionality may be extended dynamically. Packet programs are written in our special purpose programming language PLAN, the Packet Language for Active Networks, while dynamic router extensions are written in OCaml, a dialect of ML. Currently, PLANet routers run as byte-code-interpreted Linux user-space applications, and support Ethernet and IP as link layers. PLANet achieves respectable performance on standard networking operations: on 300 MHz Pentium-II{\textquoteright}s attached to 100 Mbps Ethernet, PLANet can route 48 Mbps and switch over 5000 packets per second. We demonstrate the utility of PLANet{\textquoteright}s activeness by showing experimentally how it can nontrivially improve application and aggregate network performance in congested conditions},
	keywords = {100 Mbit/s, 300 MHz, 48 Mbit/s, active internetwork, active network architecture, active network implementation, byte-code-interpreted applications, Computer architecture, Computer languages, Computer networks, congested conditions, dynamic programming, dynamic router extensions, Ethernet, Ethernet networks, INFORMATION SCIENCE, Internet, Internet-like services, internetworking, IP, IP networks, link layers, Linux user-space applications, Local area networks, ML dialect, Network performance, networking operations, OCaml, Packet Language for Active Networks, packet programs, packet switching, Pentium-II, performance, performance evaluation, PLAN, PLANet, Planets, programmability features, programming languages, router functionality, special purpose programming language, Switches, telecommunication network routing, Transport protocols, Web and internet services},
	isbn = {0-7803-5417-6},
	doi = {10.1109/INFCOM.1999.751668},
	author = {Hicks, Michael W. and Moore,J. T and Alexander,D. S and Gunter,C. A and Nettles,S. M}
}
@article {16769,
	title = {Techniques for update handling in the enhanced client-server DBMS},
	journal = {IEEE Transactions on Knowledge and Data Engineering},
	volume = {10},
	year = {1998},
	month = {1998/06//May},
	pages = {458 - 476},
	abstract = {The Client-Server computing paradigm has significantly influenced the way modern Database Management Systems are designed and built. In such systems, clients maintain data pages in their main-memory caches, originating from the server{\textquoteright}s database. The Enhanced Client-Server architecture takes advantage of all the available client resources, including their long-term memory. Clients can cache server data into their own disk units if these data are part of their operational spaces. However, when updates occur at the server, a number of clients may need to not only be notified about these changes, but also obtain portions of the updates as well. In this paper, we examine the problem of managing server imposed updates that affect data cached on client disk managers. We propose a number of server update propagation techniques in the context of the Enhanced Client-Server DBMS architecture, and examine the performance of these strategies through detailed simulation experiments. In addition, we study how the various settings of the network affect the performance of these policies},
	keywords = {client disk managers, client resources, client-server computing paradigm, client-server systems, Computational modeling, Computer architecture, concurrency control, data pages, Database systems, distributed databases, enhanced client-server DBMS, Hardware, Local area networks, long-term memory, main-memory caches, Network servers, operational spaces, Personal communication networks, server update propagation techniques, Transaction databases, update handling, Workstations, Yarn},
	isbn = {1041-4347},
	doi = {10.1109/69.687978},
	author = {Delis,A. and Roussopoulos, Nick}
}
@conference {15680,
	title = {Threshold-based admission control for multi-class video-on-demand systems},
	booktitle = {Performance, Computing and Communications, 1998. IPCCC {\textquoteright}98., IEEE International},
	year = {1998},
	month = {1998/02/16/18},
	pages = {154 - 160},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {The next generation of distributed digital video-on-demand (VoD) systems will use admission control tests to ensure that users receive predictable and guaranteed service. If the system cannot support a new request then that request is blocked This paper presents an analytical model to evaluate unified admission control strategies for distributed VoD systems with multiple video classes. We prove that there exists a computationally efficient technique to determine the blocking probabilities for newly arriving requests. Through numerical analysis we show the effect of different admission control policies on overall system blocking rates},
	keywords = {Admission control, admission control tests, analytical model, Analytical models, blocking probabilities, buffer storage, Computer architecture, distributed digital VoD systems, File servers, guaranteed service, High-speed networks, interactive video, Motion pictures, multi-class video-on-demand systems, multimedia systems, Network servers, newly arriving requests, numerical analysis, Predictive models, probability, recursive algorithm, system blocking rates, telecommunication congestion control, threshold-based admission control, unified admission control},
	isbn = {0-7803-4468-5},
	doi = {10.1109/PCCC.1998.659937},
	author = {Mundur, Padma and Sood,A. and Simon,R.}
}
@conference {12092,
	title = {A secure and reliable bootstrap architecture},
	booktitle = {, 1997 IEEE Symposium on Security and Privacy, 1997. Proceedings},
	year = {1997},
	month = {1997/05/04/7},
	pages = {65 - 71},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {In a computer system, the integrity of lower layers is typically treated as axiomatic by higher layers. Under the presumption that the hardware comprising the machine (the lowest layer) is valid, the integrity of a layer can be guaranteed if and only if: (1) the integrity of the lower layers is checked and (2) transitions to higher layers occur only after integrity checks on them are complete. The resulting integrity {\textquotedblleft}chain{\textquotedblright} inductively guarantees system integrity. When these conditions are not met, as they typically are not in the bootstrapping (initialization) of a computer system, no integrity guarantees can be made, yet these guarantees are increasingly important to diverse applications such as Internet commerce, security systems and {\textquotedblleft}active networks{\textquotedblright}. In this paper, we describe the AEGIS architecture for initializing a computer system. It validates integrity at each layer transition in the bootstrap process. AEGIS also includes a recovery process for integrity check failures, and we show how this results in robust systems},
	keywords = {active networks, AEGIS architecture, bootstrap architecture, Computer architecture, computer bootstrapping, data integrity, Distributed computing, Hardware, hardware validity, initialization, integrity chain, integrity check failures, Internet, Internet commerce, IP networks, Laboratories, lower-layer integrity, Microprogramming, Operating systems, recovery process, reliability, robust systems, Robustness, Security, security of data, software reliability, system integrity guarantees, system recovery, transitions, Virtual machining},
	isbn = {0-8186-7828-3},
	doi = {10.1109/SECPRI.1997.601317},
	author = {Arbaugh, William A. and Farber,D. J and Smith,J. M}
}
@article {11922,
	title = {MARUTI at ARDEC.},
	year = {1996},
	month = {1996/07/11/},
	institution = {University of Maryland, College Park},
	abstract = {This is the final report of the effort undertaken at the University of Maryland, sponsored by DARPA under the DSSA (Domain Specific Software Architectures) program. The activities reported here required an active cooperation and collaboration of the US Army ARDEC (Automation and Robotics Laboratory) and the University of Maryland (Computer Science Department). The principal investigators have been developing a hard real time operating system, MARUTI, at the University of Maryland. The goal of this effort was to demonstrate the applicability and usefulness of this operating system for exercising PID control at high frequency on the ATB1000 testbed which has been used to simulate a gun turret. A MARUTI based PID controller which operates at 200 HZ and 400 HZ was successfully implemented to demonstrate this feasibility.},
	keywords = {*OPERATING SYSTEMS(COMPUTERS), Computer architecture, COMPUTER PROGRAMMING AND SOFTWARE, CONTROL, Cooperation, DSSA(DOMAIN SPECIFIC SOFTWARE ARCHITECTURE), GUN TURRETS., HIGH FREQUENCY, Laboratories, REAL TIME, ROBOTICS, TEST BEDS},
	url = {http://stinet.dtic.mil/oai/oai?\&verb=getRecord\&metadataPrefix=html\&identifier=ADA315086},
	author = {Agrawala, Ashok K. and Tripathi,Satish K}
}
@conference {14760,
	title = {Dynamic program instrumentation for scalable performance tools},
	booktitle = {Scalable High-Performance Computing Conference, 1994., Proceedings of the},
	year = {1994},
	month = {1994/05//},
	pages = {841 - 850},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Presents a new technique called {\textquoteleft}dynamic instrumentation{\textquoteright} that provides efficient, scalable, yet detailed data collection for large-scale parallel applications. Our approach is unique because it defers inserting any instrumentation until the application is in execution. We can insert or change instrumentation at any time during execution by modifying the application{\textquoteright}s binary image. Only the instrumentation required for the currently selected analysis or visualization is inserted. As a result, our technique collects several orders of magnitude less data than traditional data collection approaches. We have implemented a prototype of our dynamic instrumentation on the CM-5, and present results for several real applications. In addition, we include recommendations to operating system designers, compiler writers, and computer architects about the features necessary to permit efficient monitoring of large-scale parallel systems},
	keywords = {Application software, binary image, compiler writing, Computer architecture, Computer displays, Computerized monitoring, Concurrent computing, data acquisition, data collection, data visualisation, Data visualization, dynamic program instrumentation, efficient monitoring, executing program, Instruments, large-scale parallel applications, Large-scale systems, operating system design, Operating systems, parallel programming, program analysis, program diagnostics, program visualization, Programming profession, Sampling methods, scalable performance tools, software tools},
	isbn = {0-8186-5680-8},
	doi = {10.1109/SHPCC.1994.296728},
	author = {Hollingsworth, Jeffrey K and Miller, B. P and Cargille, J.}
}
@article {16795,
	title = {Performance comparison of three modern DBMS architectures},
	journal = {IEEE Transactions on Software Engineering},
	volume = {19},
	year = {1993},
	month = {1993/02//},
	pages = {120 - 138},
	abstract = {The introduction of powerful workstations connected through local area networks (LANs) inspired new database management system (DBMS) architectures that offer high performance characteristics. The authors examine three such software architecture configurations: client-server (CS), the RAD-UNIFY type of DBMS (RU), and enhanced client-server (ECS). Their specific functional components and design rationales are discussed. Three simulation models are used to provide a performance comparison under different job workloads. Simulation results show that the RU almost always performs slightly better than the CS, especially under light workloads, and that ECS offers significant performance improvement over both CS and RU. Under reasonable update rates, the ECS over CS (or RU) performance ratio is almost proportional to the number of participating clients (for less than 32 clients). The authors also examine the impact of certain key parameters on the performance of the three architectures and show that ECS is more scalable that the other two},
	keywords = {client-server, Computational modeling, Computer architecture, database management systems, DBMS architectures, design rationales, functional components, Indexes, Local area networks, Military computing, Packaging, Performance analysis, performance evaluation, RAD-UNIFY type, simulation models, simulation results, Software architecture, software architecture configurations, software engineering, Throughput, Workstations},
	isbn = {0098-5589},
	doi = {10.1109/32.214830},
	author = {Delis,A. and Roussopoulos, Nick}
}
@article {15004,
	title = {Optimal Systolic Designs for the Computation of the Discrete Hartley and the Discrete Cosine Transforms},
	year = {1988},
	month = {1988///},
	institution = {Institute for Systems Research, University of Maryland, College Park},
	abstract = {In this paper, we propose new algorithms for computing the Discrete Hartley and the Discrete Cosine Transform. The algorithms are based on iterative applications of the modified small n algorithms of DFT. The one dimensional transforms are mapped into two dimensions first and then implemented on two dimensional systolic arrays. Pipelined bit serial architectures operating on left to right LSB to MSB binary arithmetic is the basis of the hardware design. Different hardware schemes for implementing these transforms are studied. We show that our schemes achieve a substantial speed-up over existing schemes.},
	keywords = {*ALGORITHMS, *BINARY ARITHMETIC, Computer architecture, DCT(DISCRETE COSINE TRANSFORM), DISCRETE FOURIER TRANSFORMS, ITERATIONS, NUMERICAL MATHEMATICS, TWO DIMENSIONAL},
	url = {http://stinet.dtic.mil/oai/oai?\&verb=getRecord\&metadataPrefix=html\&identifier=ADA452389},
	author = {Chakrabarti,Chaitali and JaJa, Joseph F.}
}
@article {16751,
	title = {SEES{\textemdash}A Software testing Environment Support System},
	journal = {IEEE Transactions on Software Engineering},
	volume = {SE-11},
	year = {1985},
	month = {1985/04//},
	pages = {355 - 366},
	abstract = {SEES is a database system to support program testing. The program database is automatically created during the compilation of the program by a compiler built using the YACC compiler-compiler.},
	keywords = {Computer architecture, Database systems, Error correction, Program processors, Programming profession, Relational databases, Software testing, software tools, Workstations, Writing},
	isbn = {0098-5589},
	doi = {10.1109/TSE.1985.232225},
	author = {Roussopoulos, Nick and Yeh,R. T}
}
