@conference {18017,
	title = {Arbitrate-and-move primitives for high throughput on-chip interconnection networks},
	booktitle = {Circuits and Systems, 2004. ISCAS {\textquoteright}04. Proceedings of the 2004 International Symposium on},
	volume = {2},
	year = {2004},
	month = {2004/05//},
	pages = {II - 441-4 Vol.2 - II - 441-4 Vol.2},
	abstract = {An n-leaf pipelined balanced binary tree is used for arbitration of order and movement of data from n input ports to one output port. A novel arbitrate-and-move primitive circuit for every node of the tree, which is based on a concept of reduced synchrony that benefits from attractive features of both asynchronous and synchronous designs, is presented. The design objective of the pipelined binary tree is to provide a key building block in a high-throughput mesh-of-trees interconnection network for Explicit Multi Threading (XMT) architecture, a recently introduced parallel computation framework. The proposed reduced synchrony circuit was compared with asynchronous and synchronous designs of arbitrate-and-move primitives. Simulations with 0.18 mu;m technology show that compared to an asynchronous design, the proposed reduced synchrony implementation achieves a higher throughput, up to 2 Giga-Requests per second on an 8-leaf binary tree. Our circuit also consumes less power than the synchronous design, and requires less silicon area than both the synchronous and asynchronous designs.},
	keywords = {8, arbiter, arbitrate-and-move, architecture;, asynchronous, balanced, binary, circuit, circuit;, circuits;, consumption;, data, explicit, interconnection, interconnections;, leaf, mesh-of-trees, multi-threading;, Multithreading, n-leaf, network;, pipeline, pipelined, power, primitive, processing;, reduced, simulation;, structures;, synchronous, synchrony, system-on-chip;, tree, tree;},
	doi = {10.1109/ISCAS.2004.1329303},
	author = {Balkan,A.O. and Gang Qu and Vishkin, Uzi}
}
@article {11913,
	title = {Rover: scalable location-aware computing},
	journal = {Computer},
	volume = {35},
	year = {2002},
	month = {2002/10//},
	pages = {46 - 53},
	abstract = {All the components necessary for realizing location-aware computing are available in the marketplace today. What has hindered the widespread deployment of location-based systems is the lack of an integration architecture that scales with user populations. The authors have completed the initial implementation of Rover, a system designed to achieve this sort of integration and to automatically tailor information and services to a mobile user{\textquoteright}s location. Their studies have validated Rover{\textquoteright}s underlying software architecture, which achieves system scalability through high-resolution, application-specific resource scheduling at the servers and network. The authors believe that this technology will greatly enhance the user experience in many places, including museums, amusement and theme parks, shopping malls, game fields, offices, and business centers. They designed the system specifically to scale to large user populations and expect its benefits to increase with them.},
	keywords = {amusement, application-specific, architecture;, automation;, business, business;, computing;, data, entertainment;, handheld, humanities;, integration, LAN;, location-aware, malls;, mobile, museums;, office, parks;, processing;, resource, Rover;, scalability;, scalable, scheduling;, shopping, software, system, theme, units;, user;, wireless},
	isbn = {0018-9162},
	doi = {10.1109/MC.2002.1039517},
	author = {Banerjee,S. and Agarwal,S. and Kamel,K. and Kochut, A. and Kommareddy,C. and Nadeem,T. and Thakkar,P. and Trinh,Bao and Youssef,A. and Youssef, M. and Larsen,R.L. and Udaya Shankar,A. and Agrawala, Ashok K.}
}
@article {15047,
	title = {VLSI architectures for multidimensional transforms},
	journal = {Computers, IEEE Transactions on},
	volume = {40},
	year = {1991},
	month = {1991/09//},
	pages = {1053 - 1057},
	abstract = {The authors propose a family of VLSI architectures with area-time tradeoffs for computing (<e1>N</e1> times;<e1>N</e1> times; . . . times;<e1>N</e1>) <e1>d</e1>-dimensional linear separable transforms. For fixed-precision arithmetic with <e1>b</e1> bits, the architectures have an area <e1>A</e1>=<e1>O</e1>(<e1>N</e1><sup>d+2a</sup>) and computation time <e1>T</e1>=<e1>O</e1>(<e1>dN</e1><sup>d/2-a</sup><e1>b </e1>), and achieve the <e1>AT</e1><sup>2</sup> bound of <e1>AT</e1><sup>2</sup>=<e1>O</e1>(<e1>n</e1><sup>2</sup><e1>b</e1> <sup>2</sup>) for constant <e1>d</e1>, where <e1>n</e1>=<e1>N</e1><sup>d </sup> and <e1>O</e1> lt;<e1>a</e1> les;<e1>d</e1>/2},
	keywords = {architecture;, architectures;, arithmetic;, complexity;, computational, Computer, digital, fixed-precision, linear, multidimensional, separable, transforms;, VLSI},
	isbn = {0018-9340},
	doi = {10.1109/12.83648},
	author = {Chakrabarti,C. and JaJa, Joseph F.}
}
