Circuit architecture for reduced-synchrony on-chip interconnect
| Title | Circuit architecture for reduced-synchrony on-chip interconnect |
| Publication Type | Patents |
| Year of Publication | 2004 |
| Authors | Vishkin U, Nuzman JF |
| Secondary Authors | University of Maryland C P |
| Patent Version Number | 10/166,008 |
| Date Published | 2004/07/27/ |
| Abstract | The invention relates to an interconnect, and to interconnect architecture, for communicating between processing elements and memory modules in a computer system comprising on-chip parallel computation, in order to reduce the tight synchrony that is required by important components of most present computers. |
| URL | http://www.google.com/patents?id=RRUSAAAAEBAJ |